Re: Analysis of New CCIE Checklists

Well I think this is a very good thing for the CCIE candidates out
there right now! This means that you can have a much more focused
study. The traditional BP has always been very vague to say the
least. With the detailed blueprint, they are coming out and telling
you pretty specifically what you need to know. I think this is a
great thing! Use this to your advantage, and do not even think of
showing up for the lab unless you can go down that checklist and check
every single thing off your list!

On Sun, Mar 28, 2010 at 6:39 AM, Muzammil Malick <malickmuz_at_gmail.com> wrote:
> What does this all mean though?
> The way I see it, I should just carry on preparing as though I had never
> seen this. My reasoning?
> A previous poster, Ivan, mentioned that he was caught out by OER. It was
> clearly stated on the original blueprint and npw it is missing.
> Also SRR was specifically stated on the original and if a typo can be made
> to WRR then I am sure they can miss out OER
> by mistake. I also cannot see that they would leave out BSR on the lab when
> it is an alternative to AUTORP with listener in PIM
> Sparse.
>
>
>
>
> On 28 March 2010 04:19, Marko Milivojevic <markom_at_ipexpert.com> wrote:
>
>> Hello everyone,
>>
>> I just wanted to share with you that we at IPexpert just finished
>> comparing published Blueprints, new Checklists and published our
>> finding on our blog here:
>>
>>
>> http://blog.ipexpert.com/cisco-announces-detailed-checklist-for-multiple-ccie-tracks/
>>
>> Best regards from IPexpert team - enjoy your studies!
>>
>> --
>> Marko Milivojevic - CCIE #18427
>> Senior Technical Instructor - IPexpert
>>
>> YES! We include 400 hours of REAL rack
>> time with our Blended Learning Solution!
>>
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>>
>> Blogs and organic groups at http://www.ccie.net
>>
>> _______________________________________________________________________
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>
>
> Blogs and organic groups at http://www.ccie.net
>
> _______________________________________________________________________
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>
>
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>
>
>

-- 
Regards,
Joe Astorino - CCIE #24347
Sr. Technical Instructor - IPexpert
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