Re: Analysis of New CCIE Checklists

What does this all mean though?
The way I see it, I should just carry on preparing as though I had never
seen this. My reasoning?
A previous poster, Ivan, mentioned that he was caught out by OER. It was
clearly stated on the original blueprint and npw it is missing.
Also SRR was specifically stated on the original and if a typo can be made
to WRR then I am sure they can miss out OER
by mistake. I also cannot see that they would leave out BSR on the lab when
it is an alternative to AUTORP with listener in PIM
Sparse.

On 28 March 2010 04:19, Marko Milivojevic <markom_at_ipexpert.com> wrote:

> Hello everyone,
>
> I just wanted to share with you that we at IPexpert just finished
> comparing published Blueprints, new Checklists and published our
> finding on our blog here:
>
>
> http://blog.ipexpert.com/cisco-announces-detailed-checklist-for-multiple-ccie-tracks/
>
> Best regards from IPexpert team - enjoy your studies!
>
> --
> Marko Milivojevic - CCIE #18427
> Senior Technical Instructor - IPexpert
>
> YES! We include 400 hours of REAL rack
> time with our Blended Learning Solution!
>
> Mailto: markom_at_ipexpert.com
> Telephone: +1.810.326.1444
> Fax: +1.810.454.0130
> Web: http://www.ipexpert.com/
>
>
> Blogs and organic groups at http://www.ccie.net
>
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Received on Sun Mar 28 2010 - 11:39:54 ART