From: Scott Vermillion (scott_ccie_list@it-ag.com)
Date: Sun Mar 02 2008 - 02:42:26 ARST
Hey Frog,
I'm not familiar with the exact application referenced in your first
statement there, but "station clock" generally refers to some single
reference from which many other clocks can be derived, so that wouldn't
really be surprising. In the telco world, it's not uncommon for a BITS
clock to be a T1 or E1 signal that ultimately (directly, in some cases) has
traceability back to a Stratum 1 source. The T1/E1 does not carry payload
data; it's just a source of reference by way of its predictable transitions
from one logical state to the other (actually there's more to it, but you
can google BITS if interested in the gory details). It's been a while since
I had my hands on any of the ONS platforms, but I believe those chassis
include a BITS T-1 input option (I'm all but certain of it, as I can pretty
clearly recall provisioning a 15454 ring to accept exactly that as a backup
reference several years back). And so you've got one little old 1.544 Mbps
clock source driving a box that packs OC-192 optical carriers going both
east and west! Unintuitive, but true.
I'd need further clarification on the HSSI thing you mention. I do have
experience (none recent) with that stuff and I don't recall any 2 megs clock
option per se, but again, we could be talking about an E1 BITS driving the
box or something. Below is some interesting stuff on HSSI timing (comments
follow)...
_____
http://cio.cisco.com/warp/public/459/8.html
3.4 Timing:
Source timing is defined as timing waveforms generated at a transmitter.
Destination timing is defined as timing waveforms incident at a receiver.
Pulse widths are measured between 50% points of the final pulse amplitude.
The leading edge of the timing pulse shall be defined as the boundary
between deassertion and assertion. The trailing edge of the timing pulse
shall be defined as the boundary between assertion and deassertion. RT, TT,
and ST minimum positive source timing pulse width shall be 7.7 ns. This
allows a source duty cycle tolerance of +/- 10%. This value is obtained
from:
10% = ((9.61 ns - 7.7 ns)/19.23 ns) x 100%
where:
19.23 ns = 1 / (52 Mbps)
9.61 ns = 19.23 ns * 1/2 cycle
Data will change to its new state within +/- 3 ns of the leading edge of the
source timing pulse.
RT, TT, and ST minimum positive destination timing pulse width shall be 6.7
ns. Data will change to its new state within +/- 5 ns of the leading edge of
the destination timing pulse. These numbers allow for transmission
distortion elements of 1.0 ns of pulse width distortion and 2.0 ns of clock
to data skew. This leaves 1.7 ns for receiver setup time.
The data will be considered valid on the trailing edge. Thus, transmitters
clock data out on the leading edge, and receivers clock data in on the
trailing edge. This allows an acceptance window for clock-data skew error.
The delay from the ST port to the TT port within the DTE shall be less than
25 ns. The DCE must be able to tolerate a delay of at least 100 ns between
its ST port and its TT port. This allows for a 75 ns delay for 15 meters of
cable.
RT and ST may be gapped. In the event they become disabled by the DCE, RT
disabling must not occur until 23 clock pulses after the last valid data on
RD, and ST disabling must not occur until 1 clock pulse after the last valid
data on SD. The definition of valid data is application dependent and not a
subject of this specification.
_____
So the most interesting thing from the above is: "The data will be
considered valid on the trailing edge." What this means is when the clock
falls, the data lead will be sampled and determined to be in either a one or
a zero state. This is classic serial clocking. Thus, your clock rate is
very directly tied to your data rate at the interface level (and so you
wouldn't have a 2 meg clock on an interface operating which is operating at
52 Mbps - at least not down at the interface level). Where those interface
clocks are themselves derived from can be another matter altogether, though.
You can go way far down into the weeds on this stuff, but it's mostly beyond
what your typical network engineer (even CCIE) needs to be concerned with.
I think I've been engaged in enough off topic on the list over the weekend,
so unicast me if you're interested in further discussion on serial
timing/clocking. It's a personal favorite topic from my WAN days and one
I'd likely enjoy dusting off after all these years...
Regards,
Scott
-----Original Message-----
From: nobody@groupstudy.com [mailto:nobody@groupstudy.com] On Behalf Of
Radioactive Frog
Sent: Saturday, March 01, 2008 8:42 PM
To: Scott Vermillion
Cc: Sadiq Yakasai; Santi; John; ccielab@groupstudy.com
Subject: Re: hdlc clock rate
I have seen 2 megs station clock feed even the link speed was 6 megs using a
HWIC2T cards.
Check the specification of the HSSI port. IT takes 2 megs clock but can
support port speed upto 52 megs.
So ,.. still clock rate vs data-rate is unclear!
Frog
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