From: Sami (sy1977@gmail.com)
Date: Wed Jun 21 2006 - 15:33:03 ART
Group,
When I try to delete IPV6 prefix list, router reboots everytime... Have
someone faced this kind of problem ?
R2#conf t
Enter configuration commands, one per line. End with CNTL/Z.
R2(config)#no ipv6 prefix-list BB2 seq 5 deny ::/0 ge 64
%ALIGN-1-FATAL: Corrupted program counter 17:58:24 UTC Wed Jun 21 2006
pc=0x0 , ra=0x429DE8A0 , sp=0x4615F1D8
%ALIGN-1-FATAL: Corrupted program counter 17:58:25 UTC Wed Jun 21 2006
pc=0x0 , ra=0x429DE8A0 , sp=0x4615F1D8
17:58:25 UTC Wed Jun 21 2006: TLB (load or instruction fetch) exception,
CPU signal 10, PC = 0x0
-Traceback=
$0 : 00000000, AT : 45410000, v0 : 00000000, v1 : 00000000
a0 : 46DAD34C, a1 : 00000000, a2 : 46B74A34, a3 : 00000000
t0 : 00000018, t1 : 3400FF01, t2 : 3400E100, t3 : FFFF00FF
t4 : 4008ED10, t5 : 45A16148, t6 : 45A16144, t7 : 45A16140
s0 : 46B74A34, s1 : 46DAD34C, s2 : 46B75E5C, s3 : 00000002
s4 : 458BB3D0, s5 : 458C0000, s6 : 458BB5F0, s7 : 46B95DB0
t8 : 4615F250, t9 : 00000000, k0 : 46D7E6B4, k1 : 423305C0
gp : 4541D04C, sp : 4615F1D8, s8 : 45100000, ra : 429DE8A0
EPC : 00000000, ErrorEPC : BFC00E8C, SREG : 3400FF03
MDLO : 00000000, MDHI : 00000002, BadVaddr : 00000000
Cause 00000008 (Code 0x2): TLB (load or instruction fetch) exception
Writing crashinfo to flash:crashinfo_20060621-175825
17:58:25 UTC Wed Jun 21 2006: TLB (load or instruction fetch) exception,
CPU signal 10, PC = 0x0
-Traceback=
$0 : 00000000, AT : 45410000, v0 : 00000000, v1 : 00000000
a0 : 46DAD34C, a1 : 00000000, a2 : 46B74A34, a3 : 00000000
t0 : 00000018, t1 : 3400FF01, t2 : 3400E100, t3 : FFFF00FF
t4 : 4008ED10, t5 : 45A16148, t6 : 45A16144, t7 : 45A16140
s0 : 46B74A34, s1 : 46DAD34C, s2 : 46B75E5C, s3 : 00000002
s4 : 458BB3D0, s5 : 458C0000, s6 : 458BB5F0, s7 : 46B95DB0
t8 : 4615F250, t9 : 00000000, k0 : 46D7E6B4, k1 : 423305C0
gp : 4541D04C, sp : 4615F1D8, s8 : 45100000, ra : 429DE8A0
EPC : 00000000, ErrorEPC : BFC00E8C, SREG : 3400FF03
MDLO : 00000000, MDHI : 00000002, BadVaddr : 00000000
Cause 00000008 (Code 0x2): TLB (load or instruction fetch) exception
-Traceback=
=== Flushing messages (17:58:25 UTC Wed Jun 21 2006) ===
Queued messages:
*** System received a Bus Error exception ***
signal= 0xa, code= 0x8, context= 0x45653e34
PC = 0x4008f284, Cause = 0x2020, Status Reg = 0x34008002
System Bootstrap, Version 12.4(1r) [hqluong 1r], RELEASE SOFTWARE (fc1)
Copyright (c) 2005 by cisco Systems, Inc.
Initializing memory for ECC
.
c2811 processor with 262144 Kbytes of main memory
Main memory is configured to 64 bit mode with ECC enabled
Readonly ROMMON initialized
program load complete, entry point: 0x8000f000, size: 0xc940
program load complete, entry point: 0x8000f000, size: 0xc940
This archive was generated by hypermail 2.1.4 : Sat Jul 01 2006 - 07:57:33 ART