From: Scott Morris (swm@emanon.com)
Date: Sat Jan 21 2006 - 16:31:03 GMT-3
If it's a T1 WIC with the built in CSU/DSU, then there's not really the same
concept of DCE and DTE. Either side can issue clock, the only rule is that
somoene must! In a serial cable (from a CSU to the port), there's a
particular set of pinouts that determines DCE or DTE.
In your output (2nd line) it says "TX and RX clocks detected"
HTH,
Scott
-----Original Message-----
From: nobody@groupstudy.com [mailto:nobody@groupstudy.com] On Behalf Of Nick
Griffin
Sent: Saturday, January 21, 2006 1:49 PM
To: ccielab@groupstudy.com
Subject: FR Whoes
I'm sure there's a trick to this that I'm missing. for a frame switch I have
a 3620 running 12.2(19) with 4 "FT1 Bt8360 WAN daughter cards".
I've also got a mix of 2600's and 1700's running 12.3(9e) with the same
serial cards. The problem I'm having is even getting the interfaces to come
up up. I thought I could see from a "show controller" DTE detected, or
something of the like signifying a good physical connection, but these cards
appear to behave a bit differently. At one point I've had at least a couple
of these come up up, however it's been very intermittent and inconsistent.
Anyone have these in their lab? Please see the show controller output from
the FR switch below:
Frame#sh controllers ser 0/0
Interface Serial0/0
Hardware is Quicc 68360 with Integrated FT1 CSU/DSU module TX and RX clocks
detected.
idb at 0x625A49EC, driver data structure at 0x625ACCE8 WIC interrupt reg = F
SCC Registers:
General [GSMR]=0x2:0x00000030, Protocol-specific [PSMR]=0x8 Events
[SCCE]=0x0300, Mask [SCCM]=0x001F, Status [SCCS]=0x0003 Transmit on Demand
[TODR]=0x0, Data Sync [DSR]=0x7E7E Interrupt Registers:
Config [CICR]=0x00C9CF00, Pending [CIPR]=0x00000000
Mask [CIMR]=0xE0004400, In-srv [CISR]=0x00000000
SDMA Registers:
[SDSR]=0x00, [SDAR]=0x000105EB, [SDCR]=0x0772 Command register [CR]=0x640
Port A [PADIR]=0x0000, [PAPAR]=0xFFFF
[PAODR]=0x0000, [PADAT]=0xA5FE
Port B [PBDIR]=0x0013FE, [PBPAR]=0x00000E
[PBODR]=0x000000, [PBDAT]=0x03CC5C Port C [PCDIR]=0x0002,
[PCPAR]=0x000C
[PCSO]=0x00A0, [PCDAT]=0x0FFD, [PCINT]=0x0001 Receive Ring
rmd(3C010420): status 9000 length 2 address 3C1AEA4
rmd(3C010428): status 9000 length 2 address 3C1B524
rmd(3C010430): status 9000 length 2 address 3C187A4
rmd(3C010438): status 9000 length 2 address 3C18E24
rmd(3C010440): status 9000 length 2 address 3C194A4
rmd(3C010448): status 9000 length 2 address 3C19B24
rmd(3C010450): status B000 length 2 address 3C1A824 Transmit Ring
tmd(3C010458): status 0 length 0 address 0
tmd(3C010460): status 0 length 0 address 0
tmd(3C010468): status 0 length 0 address 0
tmd(3C010470): status 0 length 0 address 0
tmd(3C010478): status 0 length 0 address 0
tmd(3C010480): status 0 length 0 address 0
tmd(3C010488): status 2000 length 0 address 0
tx_limited=1(2)
SCC GENERAL PARAMETER RAM (at 0x3C010C00) Rx BD Base [RBASE]=0x420, Fn Code
[RFCR]=0x18 Tx BD Base [TBASE]=0x458, Fn Code [TFCR]=0x18 Max Rx Buff Len
[MRBLR]=1548 Rx State [RSTATE]=0x18008000, BD Ptr [RBPTR]=0x450 Tx State
[TSTATE]=0x0, BD Ptr [TBPTR]=0x458
SCC HDLC PARAMETER RAM (at 0x3C010C38)
CRC Preset [C_PRES]=0xFFFF, Mask [C_MASK]=0xF0B8
Errors: CRC [CRCEC]=0, Aborts [ABTSC]=0, Discards [DISFC]=0 Nonmatch Addr
Cntr [NMARC]=0 Retry Count [RETRC]=0 Max Frame Length [MFLR]=1608 Rx Int
Threshold [RFTHR]=0, Frame Cnt [RFCNT]=65523 User-defined Address
0000/0000/0000/0000 User-defined Address Mask 0x0000
buffer size 1524
QUICC SCC specific errors:
0 input aborts on receiving flag sequence 0 throttles, 0 enables 0 overruns
0 transmitter underruns 0 transmitter CTS losts 0 aborted short frames
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