From: Balaji Siva (bsivasub@gmail.com)
Date: Sat Feb 19 2005 - 02:55:50 GMT-3
Hi guys,
This is probably been beaten to death. I did try to find the
information but I didn't want to waste too much time trying to find
it.
Here is the question
When I just configured CIR = 64000 bps , my bc gets assigned 64000
bits automagically but the interval (Tc) is 125 ms
Now that doesn't make sense. Is this just a cosmetic issue ? In the
lab, I am guessing it is good idea to configure BC explictly as 1/8 of
CIR ..correct ?
Interface Se1/0.2
Access Target Byte Sustain Excess Interval Increment Adapt
VC List Rate Limit bits/int bits/int (ms) (bytes) Active
103 64000 1000 64000 0 125 1000
R6(config)#map-class frame-relay ccie
R6(config-map-class)#frame-relay bc 8000
R6(config-map-class)#end
R6#show traffic-shape
Interface Se1/0.1
Access Target Byte Sustain Excess Interval Increment Adapt
VC List Rate Limit bits/int bits/int (ms) (bytes) Active
101 128000 2000 128000 0 125 2000 -
Interface Se1/0.2
Access Target Byte Sustain Excess Interval Increment Adapt
VC List Rate Limit bits/int bits/int (ms) (bytes) Active
103 64000 1000 8000 0 125 1000 -
R6#
You can see the same issue for dlci 101 (128000)
Thanks
Balaji
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