From: Howard C. Berkowitz (hcb@xxxxxxxxxxxx)
Date: Sat May 04 2002 - 21:50:42 GMT-3
At 3:56 PM -0700 5/4/02, Harish DV/peakxv wrote:
>Even I know few other vendors , but the max is 4T1s. Can someone explain
>why is this limitation?.
>
>http://www.rad.com/products/family/imx-4t1/imx-4t1.htm
>
>Harish
>
>
>Does anyone know definitely the max # of T1's (Syncrhonous Serial)
>interfaces that can be inverse multiplexed using Multilink PPP. I checked
>the Cisco Web site and I saw 4 ?
>
>http://www.cisco.com/univercd/cc/td/doc/product/software/ios120/12cgcr/dial_
>
>c/dcppp.htm#xtocid1172540
>
>Thanks...
>
>Steve
I can't give a definitive answer, but I can give some that apply in
specific cases.
On the AGS and, I believe, early 7000s, one low-level processor
served four lines of the serial interface. It would be reasonable to
constrain the bundle to that which can be local to a single chip.
Four T1s make up a T2, and there is considerable experience and
theory in synchronizing four T1 streams into a T2. This, of course,
is layer 1, not MLPPP.
I'm reasonably certain that Tiara Networks makes/made an external
MLPPP box that would take considerably more than 4 T1s, and it was
targeted against this Cisco restriction. So, I suspect the Cisco
reasons may be historical compatibility.
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